Job Description

Senior SoC Design Engineer

Job Title: Senior SoC Design Engineer

Location: On Site - San Jose, California, United States

Talently provided pay range

This range is provided by Talently. Your actual pay will be based on your skills and experience talk with your recruiter to learn more.

Base pay range

$180,000.00/yr - $230,000.00/yr

About the Technology Company / The Opportunity

Join a pioneering technology company dedicated to building the infrastructure powering the next decade of AI. Leveraging deep expertise in semiconductors, AI systems, and software innovation, our client is committed to enabling smarter devices and sustainable data centers. As a Senior SoC Design Engineer, you'll collaborate with a worldclass team of visionaries and problemsolvers to push the boundaries of AI hardwaremaking a meaningful, global impact in a fastgrowing environment.

Responsibilities

• Integrate multiple IP blocks and subsystems to develop comprehensive SystemonChip (SoC) solutions ensuring proper connectivity and signal routing.
• Develop and maintain toplevel RTL integration structures including clock, reset, Design for Testability (DFT), power management, and systemlevel connectivity.
• Collaborate closely with IP design teams to successfully incorporate inhouse, commercial, and opensource IP into SoC designs.
• Create and implement detailed test plans for integration, working alongside verification engineers to achieve robust coverage and closure.
• Develop and optimize scripts and automation tools to streamline SoC assembly and integration processes.
• Document integration procedures, generating design specifications, guidelines, and verification reports for engineering teams.
• Partner with Physical Design teams to ensure integration supports efficient placeandroute implementation and timing closure.

Must-Have Skills

• Bachelor's or Masters degree in Electrical/Computer Engineering or a related discipline.
• 7+ years of handson experience in digital design with Verilog or SystemVerilog.
• Proven experience integrating complex SoCs with diverse IP blocks including open source IP, processor cores, AXI/AHB fabric IP, memory controllers, and highspeed interfaces.
• Expertise in designing and integrating infrastructure components such as clock, reset, DFT, monitors, and power management.
• Strong proficiency with scripting languages (Python, Perl, Tcl) for automation and workflow optimization.
• Skilled with EDA tools and simulation environments (ModelSim, VCS, Xcelium) for verification and synthesis.
• Exceptional analytical, communication, and debugging abilities for multiblock integration challenges.

NicetoHave Skills

• Experience integrating open source IP of variable quality into commercialgrade SoCs.
• Knowledge of current AI and edge device requirements as applied to SoC architecture.
• Background in developing and maintaining integration automation frameworks for largescale semiconductor projects.
• Familiarity with emerging standards in connectivity, power efficiency, and highspeed communication interfaces.
• Exposure to collaborative multidisciplinary engineering teams across hardware and software domains.

Seniority Level

MidSenior level

Employment Type

Fulltime

Job Function

Engineering and Design

Industries

Computer Hardware Manufacturing

Inferred from the description for this job

Medical insurance

Vision insurance

401(k)

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